APh 009: Nanofabrication

From the Caltech course catalog,

APh/EE 9 ab. Solid-State Electronics for Integrated Circuits.

6 units (2-2-2); first, second terms; six units credit for the freshman laboratory requirement. Prerequisite: Successful completion of APh/EE 9 a is a prerequisite for enrollment in APh/EE 9 b. Introduction to solid-state electronics, including physical modeling and device fabrication. Topics: semiconductor crystal growth and device fabrication technology, carrier modeling, doping, generation and recombination, pn junction diodes, MOS capacitor and MOS transistor operation, and deviations from ideal behavior. Laboratory includes computer-aided layout, and fabrication and testing of light-emitting diodes, transistors, and inverters. Students learn photolithography, and use of vacuum systems, furnaces, and device-testing equipment. Instructor: Scherer.

Special thanks to Aditya Rajagopal, my lab TA.